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Manuscript received August 18, 2014; revised November 27, 2014 and

February 11, 2015; accepted May 25, 2015. This work was supported by

the National Science Council (NSC) of Taiwan, under Grant NSC 102-

2221-E-214 -027.

The authors are with the Department of Electrical Engineering, I-Shou

University, Kaohsiung 84001, Taiwan (e-mail: chchang@isu.edu.tw;

cacheng@isu.edu.tw; enchihchang@isu.edu.tw; hlcheng@isu.edu.tw and

poen_yang@hotmail.com).

An Integrated High-Power-Factor Converter with

ZVS Transition

Chien-Hsuan Chang, Member, IEEE, Chun-An Cheng, Member, IEEE, En-Chih Chang, Hung-Liang Cheng, Member,

IEEE, and Bo-En Yang

Abstract—This paper proposes a single-phase high-powerfactor ac/dc converter with soft-switching characteristic. The circuit topology is derived by integrating a boost converter and a buck converter. The boost converter performs the function of power-factor correction (PFC) to obtain high power factor and

low current harmonics at the input line. The buck converter further regulates the dc-link voltage to provide a stable dc output voltage. Without using any active-clamp circuit or snubber circuit, the active switches of the proposed converter can achieve zero-voltage switching-on (ZVS) transition together with high power factor that satisfies the IEC 61000-3-2 standards over a wide load range from 30% to 100% rated

power. The steady-state analysis is developed and a design example is provided. A prototype circuit of 60 W was built and tested. Experimental results verify the feasibility of the proposed circuit with satisfactory performance.

Keywords—Boost converter, buck converter, power-factor

correction (PFC), zero-voltage switching-on (ZVS).

I. INTRODUCTION

Nowadays, switching-mode ac/dc converters have been

widely used in many off-line appliances, such as dc

uninterruptible power supply, telecommunications power

supply, LED driver etc. [1-2]. The increasing amount urges

researchers to develop more efficient, smaller size, and low

cost ac/dc converters. In order to meet the standards of

harmonic regulation such as IEC 61000-3-2 Class D and

IEEE 519, a power-factor corrector is usually required.

Owing to the advantages of simple circuit topology and

easy control, boost or buck-boost converters have been

widely served as power-factor correctors [3-6]. In order to

achieve unity power factor, it requires the output voltage of

both converter be higher than the amplitude of the ac line

voltage. Therefore, high-power-factor ac/dc converters

usually consist of two stages. The first one is an ac-to-dc

stage which performs the function of PFC and the second

one is a dc-to-dc stage used to supply stable dc voltage to

the load [7-10]. In spite of their good performance, the

circuit efficiency of two-stage approaches is impaired since

it takes two energy-conversion processes which inevitably

introduce some losses including switching loss, conduction

loss and magnetic core loss. Besides the two-stage

approaches, the Cuk and the Sepic converters can also

achieve high power factor and regulate the output voltage

[11-14]. The Cuk converter is a combination of boost and

buck converter and the Sepic converter is a combination of

boost and buck-boost converter. Both converters have the

advantage of simple circuit topology since they only use one

active switch and one diode. High power factor can be

achieved by operating the boost converter either at DCM or

continuous conduction mode (CCM). The buck or buckboost

converter can further regulate the output voltage of the

boost converter to obtain a smooth dc voltage. However, the

output voltage of the boost converter is usually higher than

the amplitude of the AC line voltage. Before turning on the

active switch, the output voltage is across its parasitic

capacitor. The energy stored in the parasitic capacitor is

discharged at turning on the active switch, resulting in high

switching losses and a high spike current. The boost, Cuk

and Sepic converters can also be operated at critical

conduction mode (CRM) to obtain high power factor.

Synchronous rectification (SR) technique is popularly

applied while operating these converters at CRM [15-17]. A

MOSFET is used to replace the freewheel diode, and hence

the conduction loss is effectively reduced. Furthermore, by

extending the turn-on time of the synchronous switch, the

inductor current would decline to negative. This negative

inductor current can discharge the parasitic capacitance of

the main switch to provide ZVS. However, SR technique

requires additional control circuitry to adjust the timing of

the switches. Moreover, the switching frequency is not

constant, but varies a wide range within an AC line period

while operating these converters at CRM.

In pursuit of high efficiency and high power factor,

researchers have presented many single-stage ac/dc

converters based on the integration of a PFC stage and a dcto-

dc stage [18-29]. By sharing one or two active switches,

the single-stage approaches have the advantages of less

component count, simply circuit topology and cost effective.

As compared with two-stage approaches, the circuit

efficiency is improved since only one power-conversion

process is required. Among them, some single-stage

approaches integrate a PFC converter with a full-bridge or

half-bridge resonant converters. These resonant converters

can operate with ZVS if the resonant circuits present

inductive, i.e. the switching frequency is above the resonant

frequency. Moreover, ZVS can be achieved within a wide

load range by variable-frequency control or asymmetrical

pulse-width modulation (APWM). Although, these

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topologies can effectively eliminate switching losses by

switching the active switches near the resonance frequency

to achieve ZVS, operating active switches near the

resonance frequency companies with high resonant current

and results in more conduction losses. The single-stage

approaches that integrate two PWM converters also have

some drawbacks that restrict further improving the circuit

efficiency. The major problem is that the active switches

usually operate in hard switching. An active switch that

operates at hard switching not only generates high switching

losses but also introduces high voltage and current stresses

on circuit components, resulting in poor efficiency and low

circuit stability.

The switching loss is theoretically proportional to the

switching frequency. Now that hard-switching operation has

serious switching losses in the active switches, it prevents

converters from using small magnetic components and

capacitors by increasing the switching frequency. In order to

solve the problem of hard switching, some soft-switching

techniques which adopt active-clamp circuit or snubber

circuit have been proposed [30-36]. These soft-switching

techniques have substantially eliminated the switching loss.

However, these techniques need to use additional auxiliary

switch, diode and reactive components to make the active

switches turn on at zero-voltage. It adds the circuit

complexity and overall cost. Besides, another conduction

losses resulting from the circulating current in the activeclamp

circuit would happen.

In this paper, a new ac/dc converter featuring ZVS with

simple control is presented and analyzed. This paper is

organized as follows. Section II presents the derivation of

the circuit configuration and the circuit operation for the

different operation modes. Detail circuit analysis and design

equations are provided in Section III. In Section IV, a 60-W

prototype circuit is built, and tested to verify the feasibility

of the proposed converter. Finally, some conclusions are

given in Section V.

II. CIRCUIT CONFIGURATION AND OPERATION MODES

Fig. 1 is an example of a high-power-factor ac/dc

converter with a two-stage circuit topology. It consists of a

boost converter and a buck converter. This two-stage

converter can realize high-power factor with a wide load

range. Nevertheless, both active switches of the converter

operate at hard-switching condition, resulting in high

switching losses and high current and voltage stresses.

In order to solve the problem resulting from hard

switching, a new ac/dc converter is proposed, as shown in

Fig. 2. The circuit topology is derived by relocating the

positions of the semiconductor devices in Fig. 1. Here,

MOSFETs S1 and S2 play the roles of active switches and

the antiparallel diodes DS1 and DS2 are their intrinsic body

diodes, respectively. The proposed circuit mainly consists of

a low-pass filter (Lm and Cm), a diode-bridge rectifier (D1-

D4), a boost converter and a buck converter. The boost

converter is composed of Lp, DS1, S2 and Cdc and the buck

Fig. 1. Two-stage ac/dc converter.

Fig. 2. Circuit topology of the proposed ac/dc converter.

converter is composed of Lb, D5, DS2, S1 and Co. Both

converters operate at a high-switching frequency, fs. The

boost converter performs the function of PFC. When it

operates at discontinuous-conduction mode (DCM), the

average value of its inductor current in every high-switching

cycle is approximately a sinusoidal function [5]. The lowpass

filter is used to remove the high frequency current of

the inductor current. By this way, the boost converter can

waveshape the input line current to be sinusoidal and in

phase with the input line voltage. In other word, high power

factor and low total current harmonic distortion (THDi) can

be achieved. The buck converter further regulates the output

voltage of the boost converter to supply stable dc voltage to

the load. It is also deigned to operate at DCM for achieving

ZVS based on the reason that will be discussed in the final

of this section.

Two gate voltages, vGS1 and vGS2 from a half-bridge gate

driver integrated circuit (IC) are used to alternately turn S1

and S2 on and off. These voltages are complementary

rectangular-wave voltages. In order to prevent both active

switches from cross conducting, there is a short non-overlap

time defined as “dead time”. In the dead time, vGS1 and vGS2

are at a low level. Neglecting the short dead time, the duty

cycle of vGS1 and vGS2 is 0.5.

For simplifying the circuit analysis, the following

assumptions are made:

1) The semiconductor devices are ideal except for the

parasitic output capacitance of the MOSFETs.

2) The capacitances of Cdc and Co are large enough that

the dc-link voltage Vdc and the output voltage Vo can be

regarded as constant.

At steady state, the circuit operation can be divided into

eight modes in every high-frequency cycle. Fig. 3 shows the

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equivalent circuits for each of the operation modes. In these

equivalent circuits, the low-pass filter and the diode rectifier

are represented by the rectified voltage vrec. Fig. 4 illustrates

the theoretical waveforms in each mode for the case of

operating the buck converter at DCM. The circuit operation

is described as follows.

A. Mode I (t0 < t < t1)

Prior to Mode I, S1 is at “ON” state. The boost-inductor

current ip is zero and the dc-link capacitor supplies the buckinductor

current ib which flows through S1, D5, Lb and Co.

This mode starts when S1 is turned off by the gate voltage,

vGS1. The time interval of this mode is the turn-off transition.

At the beginning of this mode, ib is diverted from S1 to flow

through the output capacitors CDS1 and CDS2. CDS1 and CDS2

are charged and discharged, respectively. As the voltage

across CDS2 (vDS2) decreases to be lower than the rectified

input voltage vrec, the boost-inductor current ip starts to

increase. When vDS2 reaches -0.7 V, DS2 turns on and Mode I

ends.

B. Mode II (t1 < t < t2)

At the beginning of Mode II, voltage vDS2 is maintained at

about -0.7 V by the antiparallel diode DS2. After the short

dead time, S2 is turned on by the gate voltage, vGS2. If the

on-resistance of S2 is small enough, most of ib will flow

through S2 in the direction from its source to drain.

Neglecting this small value of vDS2, the voltage across Lb and

Lp are equal to

vb t Vo (1)

2 p rec m L v t v t V sin f t (2)

Fig. 3. Operation modes.

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where fL and Vm are the frequency and the amplitude of the

input line voltage, respectively. Since the time interval of

Mode I is very short, ib can be expressed as:

0 0 ( ) ( ) o

b b

b

V

i t i t t t

L

(3)

From (3), ib decreases from a peak value. The boost

converter is designed to operate at DCM, therefore ip

increases linearly from zero with a rising slope that is

proportional to vrec.

0 0

sin 2

( ) rec m L

p

p p

v V f t

i t t t t t

L L

(4)

In Mode II, ib is higher than ip. Current ib has two loops.

Parts of ib flow through S2 and the rest are equal to ip and

flow through the line-voltage source, diode rectifier and Lp.

This mode ends when ip rises to become higher than ib.

C. Mode III (t2 < t < t3)

In Mode III, ip is higher than ib. Current ip has two loops.

Parts of ip are equal to ib and flow into the buck converter,

while the rest flow through S2. The current direction in S2 is

naturally changed, i.e. from drain to source. The voltage and

current equations for vb, vp, ib and ip are the same as (1) –

(4). Current ib decreases continuously. On the contrary, ip

keeps increasing. Since the buck converter is designed to

operate at DCM, ib will decrease to zero at the end of this

mode.

D. Mode IV (t3 < t < t4)

In this mode, S2 remains on to carry ip. Beacuse ib is zero,

the buck converter is at “OFF” state and the output capacitor

Co supplies current to load. When S2 is turned off by the

gate voltage vGS2, Mode IV ends.

E. Mode V (t4 < t < t5)

Current ip reaches a peak value at the time instant of

turning off S2. For maintaining flux balance in Lp, ip will be

diverted from S2 to flow through CDS1 and CDS2 when S2 is

turned off. CDS1 and CDS2 are discharged and charged,

respectively. Current ib is zero at the beginning of this mode,

and will start to increase when the voltage across CDS1 (vDS1)

decreases to be lower than Vdc-Vo, that is the voltage across

Lb becomes positive. As vDS1 reaches -0.7 V, DS1 turns on

and Mode V ends.

F. Mode VI (t5 < t < t6)

At the beginning of Mode VI, vDS1 is maintained at about

-0.7 V by the antiparallel diode DS1. After the short dead

time, S1 is turned on by vGS1. If the on-resistance of S1 is

small enough, most of ip will flow through S1 in the

direction from its source to drain. Neglecting this small

value of vDS1, the voltage imposed on Lp and Lb can be

respectively expressed as

vp t vrec t Vdc Vm sin 2 fLt Vdc (5)

b dc o v t V V . (6)

For a boost converter, the dc-link voltage Vdc is higher

than the rectified voltage vrec. Neglecting the short turning

off transition of S2, ip can be expressed as:

4 4

m 2 L dc

p p

p

V sin f t V

i t i t t t

L

(7)

On the contrary, the voltage across Lb is positive to make

ib rise from zero.

4 ( ) dc o

b

b

V V

i t t t

L

(8)

In Mode VI, ip is higher than ib. There are two loops for

ip. Parts of ip flow through S1 to charge the dc-link capacitor

Cdc and the rest are equal to ib and flow into the buck

converter. This mode ends when ib rises to become higher

than ip.

G. Mode VII (t6 < t < t7)

In Mode VII, ib is higher than ip. There are two loops for

ib. Parts of ib are equal to ip and flow into the boost converter,

while the rest flow through S1. The current direction in S1 is

naturally changed, i.e. from drain to source. The voltage and

current equations for vp, vb, ip and ib are the same as (5) – (8).

Current ib increases continuously while ip keeps decreasing.

The circuit operation enters next mode as soon as ip

decreases to zero.

H. Mode VIII (t7 < t < t8)

S1 remains on and ib keeps increasing. This mode ends at

the time when vGS1 becomes a low level to turn off S1 and,

the circuit operation returns to Mode I of the next highfrequency

cycle.

Based on the circiuit operation, prior to turning on one

active switch, the output capactance is discharged to about

0.7 V by the inductor current. Then, the intrinsic body diode

of the active switch turns on to clamp the active voltage at

nearly zero voltage. By this way, each active switch

achieves ZVS operation.

The reason for operating the buck converter at DCM is

explained below. In operation Mode II, ip rises and ib

decreases. It should be noted that ip rises in proportional to

the input voltage and has a small peak in the vicinity of

zero-cross point of the input voltage. If the buck converter is

operated at continuous-conduction mode (CCM), ib could

keep higher than ip. On this condition, the circuit operation

would not enter into Mode III and Mode IV, and vDS1 is

maintain at about Vdc. When S1 is turned on, ib is diverter

from S2 to S1. CDS1 is discharged at a high voltage of Vdc,

resulting a spike current and high switching losses.

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Fig. 4. Theoretical waveforms of the proposed converter.

III. CIRCUIT ANALYSIS

According to the circuit operation in the previous section,

it can be seen that the antiparallel diode of the active switch

of one converter serves as the freewheeling diode of the

other converter. In spite of it, the feathers of the boost and

the buck converter can be retained. Therefore, the two

converters can be analyzed separately.

A. Boost-Converter-Type Power-Factor Corrector

The boost-inductor current ip increases from zero and

reaches a peak value at the end of Mode IV. In practical, the

frequency of the input line voltage, fL, is much lower than

that of the converters. It is reasonable to consider the

rectified input voltage vrec as a constant over a highfrequency

cycle. From (4), the peak values of ip can be

expressed as

4 0

2 2

2

m L m L s

p,peak

p p

V sin f t V sin f t T

i t t t

L L

(9)

where Ts is the high-frequency switching period. At the

beginning of Mode V, ip start to decrease. Eq. (7) can be

rewritten as

t . T .

L

V sin f t V

L

V sin f t T

i t s

p

m L dc

p

m L s

p 0 5

2

2

2

(10)

From (10), the duration of the interval during which ip

decreases from the peak value to zero is described by

.

V V sin f t

. T V sin f t

t t

dc m L

s m L

p,off

2

0 5 2

(11)

In order to operate the boost converter at DCM, tp,off (t)

must always be less than half of the switching period.

, 0.5 . p off s t t T (12)

Combining (11) and (12), Vdc should be high enough to

ensure DCM operation over an entire input line-frequency

cycle, as follows:

2 . dc m V V (13)

The conceptual waveform of ip is shown in Fig. 5. It is

noted that the peak values of ip follow a sinusoidal envelope.

The average value of ip over a high-frequency cycle is given

by

0 5

2

s p,off p,peak

p

s

. T t t i t

i t .

T

(14)

It results in (15) by substituting (9) and (11) into (14).

2 1

8 1 1 2

m L

p

p s

L

V sin f t

i t

L f sin f t

k

(15)

where the index k is defined as

dc .

m

k V

V

(16)

Considering the effect of diode-bridge rectification and

the low-pass filter that can remove the high-frequency

contents of ip, the input current iin is equal to the average

value of ip, as follows:

2 1

8 1 1 2

m L

in

p s

L

V sin f t

i t .

L f sin f t

k

(17)

It can be seen that iin will be close to a sinusoidal

waveform at a large value of k. In other words, Vdc should be

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high enough to have a sinusoidal input current. Using (16)

and (17), the input power can be obtained by taking average

of the instantaneous product of the input voltage and current

over one line-frequency cycle.

2

0

1 2 2

8

m

in m L in L

p s

V

P Vsin ft i td ft y

L f

(18)

(18)

where y is expressed in (19), as follows: [4]

2 3

1 2

0 2

= 1 2 1 2 1 1 1

y sin d k sin k k

sin k k

k

(18)

(19)

Assuming a circuit efficiency of , the output power can

be expressed as

2

8

m

o

p s

V

P y

L f

(20)

The root-mean-squared value of the input current is

calculated by using (17).

2

0

1 2 =

8

m

in,rms in

p s

V

I i t d ft z

L f

(21)

where z is expressed in (22), as follows: [5]

Fig. 5. Conceptual waveform of the boost-inductor current.

Fig. 6. Power factor versus k. (k =Vdc/Vm).

2

0

4 3 2

2 1

2 2 3 2 2

1 1

2 2 2 1 =

1 1 2 1

z sin d

sin

k

k k k k tan

k k k

(22)

Since the input voltage is purely sinusoidal, the power

factor defined as the ratio of input power to the product of

the root-mean-squared values of input voltage and current

can be obtained by using (18) and (21).

= 2

2

in

m

in,rms

PF P y .

V I z

(23)

The power factor as a function of k is calculated and

plotted in Fig. 6 by using (19), (22) and (23). As shown,

high power factor can be achieved at a high-valued k. From

(13), the index k should be higher than 2. In this situation,

power factor is better than 0.99.

B. Buck Converter

For DCM operation, ib rises from zero. Neglecting the

short transition of turning off S2, the rising time of ib is equal

to 0.5Ts. From (8), ib has a peak value that is equal to

,

2

dc o S

b peak

b

V V T

i

L

(24)

The current ib starts to decrease when S1 is turned off. By

using (3), the time duration for ib decreasing from the peak

value to zero is given by

, 2

dc o S

b off

o

V V T

t

V

(25)

For fulfilling DCM operation, tb,off should be less than

0.5Ts. This leads to

2 dc o V V (26)

AS shown in Fig. 4, ib is with a triangular waveform and

its average value can be derived by using (24) and (25).

, , (0.5 ) ( )

2 8

s b off b peak dc o dc s

b

s bo

T t i V V V T i

T LV

(27)

At steady-state operation, the average value of ib will be

equal to the output current.

o

b o

o

V

i I

R

(28)

Combining (27) and (28), the formula of Lb for DCM

operation is derived, as follows:

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( ) ( )

8 8

dc o dc s dc o dc

b

o o o s

V V V T V V V

L

V I P f

(29)

IV. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS

An illustrative example for driving sixty 1-W highbrightness

LEDs is provided. These LEDs are connected in

series. The rated voltage and current of each LED are 3.6 V

and 0.28 A, respectively. Table I lists the circuit

specifications. The input voltage is 110 Vrms ± 10%. The

switching frequency is 50 kHz at rated power operation. In

this design example, both converters are designed to operate

at DCM. The circuit parameters are designed as follows.

A. Parameters Design

From (13) and (26), Vdc should be limited between 2Vm to

2Vo. Taking the consideration of 10% input voltage

fluctuation, Vdc is chosen to be

360 V. dc V

In this case, k is calculated to be 2.3. From Fig. 6, the

power factor higher than 0.99 can be expected.

Assuming 95% circuit efficiency, Lp and Lb can be

calculated by using (18) and (29) respectively.

2 3

1 2

3 2

0 95 155 1 2 1 2

8 50 10 60 1

=0.76 mH ( 2 3)

p

L . k sin k k

k k

k .

3

(360 216) 360 2.14 mH.

b 8 216 0.28 50 10 L

Lm and Cm are designed to perform as a low-pass filter to

filter out the high-frequency components of the boostinductor

ip. By rule of thumb, the natural frequency of a

low-pass filter is about 1 decade below the switching

frequency. Here, the natural frequency is designed to be 5

kHz, and Lm and Cm are determined to be

2 16 mH, 0 47 μF. m m L . C .

B. Dimming operation

The LED had been tested at different power. Fig. 7 shows

its V-I curve. Based on these experimental results, the LED

voltage as a function of output power can be expressed as

3 2

0 0 0 0 0003 0 0407 2 4742 150 oV . P . P . P (30)

For dimming operation, the output voltage is adjusted to

regulate the LED current. As shown in (20), Po is functions

of y and fs. From (19), the parameter y would vary slightly

when k is in the neighbor of 2.3. Hence, it is reasonable to

assume that Po is inversely proportional to the switching

frequency. By using (29), Vdc can be expressed as

2

2 32

o o b o s

dc

V V L P f

V

(31)

Fig. 8 shows the theoretical curves of Vdc and fs versus Po.

Using (30) and (31), if the LED is dimmed from 100% to

30% rated power, the switching frequency would vary form

50 kHz to 167 kHz. The dc-link voltage and the output

voltage vary form 360 V to 336 V and 216 V to 183.1 V.

During the dimming operation, (13) and (26) are satisfied to

ensure both converters operate at DCM. In other words, the

inductor current of one converter will decline to zero before

turning off the active switch of the other converter. It

ensures the intrinsic body diode of one active switch will be

turned on to flow the inductor current when the other active

switch is turned off. By this way, ZVS operation can be

achieved within the dimming range.

A prototype circuit is built and tested. Table II lists the

circuit parameters. Since the I–V characteristic of an LED is

similar to that of a diode, a small variation in the LED

voltage will result in a significant change in its current.

Generally, constant current control with low-frequency

pulse-width modulation is usually used to realize LED

TABLE I. CIRCUIT SPECIFICATIONS.

Input Line Voltage, vin 110 Vrms±10%, 60 Hz

High Switching Frequency, fS1, f S2 50 kHz

Output Power, Po 60 W

Output Voltage, Vo 216 V (= 3.6 V 60)

Output Current, Io 0.28 A

Fig. 7. V-I curve of tested LED.

, rated value (%) o o P P

Fig. 8. Vdc and fs versus Po.

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Fig. 9. Control circuit.

dimming. However, it requires complicated circuit to

precisely detect the peak value of the pulsed LED current. In

this prototype circuit, sixty LEDs are connected in series

and then, more voltage change is needed to dim the LED. It

makes the series-connected LEDs can be easily dimmed by

voltage control. Fig. 9 shows the closed-loop control circuit

that mainly consists of a double-ended controller (L6599)

for half-bridge topology and a photocoupler (PC817). The

L6599 provides a pair of gate voltages with fixed dead time

(0.3μs) to drive both active switches. Output voltage

regulation is obtained by modulating the switching

frequency. The feedback signal of the output voltage is

transferred to pin 4 of the L6599 via the phototransistor of

the optocoupler to modulate the switching frequency. The

output voltage is varied by adjusting the variable resistor

VR1 for dimming LED.

Fig. 10 to Fig. 13 shows voltage and current waveforms

that are measured at rated output power. Fig. 10 shows the

waveforms of the input voltage, the input current and the

boost-converter current. It is seen that the boost converter

operates at DCM over an entire cycle of the line voltage.

The input current is close to a sinusoidal waveform. Besides,

the input current and the input voltage are in phase with

each other. High power factor and low THDi can be

achieved. The measured power factor and THDi are 0.995

and 9.25%, respectively. It complies with the standards of

IEC 61000-3-2 class D. Fig. 11 shows the waveforms of the

output voltage and output current. The measured values well

satisfy the theoretical prediction. The inductor-current

waveforms of both converters are shown in Fig. 12. Both

converters operate at DCM. Fig. 13 shows the voltage and

current waveforms of the active switches which are

measured at the peak point and the zero-crossing point of

the input-line voltage, respectively. As shown, both active

switches are switched on at nearly zero voltage. With ZVS

operation at both active switches, the circuit efficiency is as

high as 94.8%. It is noted that ip is almost zero at the zerocrossing

point of the AC voltage and cannot fully discharge

the output capacitance of S1 within the deadtime. When S1 is

turned on at the end of deadtime, the remaining charges in

the output capacitance rapidly flow through S1, resulting in a

spike current, as shown in Fig. 13 (b). Since the non-ZVS

operation only happens at the zero-crossing point of the AC

input, it insignificantly impairs the circuit efficiency. In

order to know how much efficiency can be improved with

proposed circuit, a two-stage boost+buck prototyped circuit

is built and tested with the same circuit specification as the

proposed circuit. At 50 kHz switching frequency, the

measure efficiency of the two-stage circuit is 90.7%.

The measured curves of power factor, THDi and circuit

efficiency over a load range from 30% to 100% rated power

are shown in Fig. 14. Power factor is close to unity over the

wide load range, while THDi increases dramatically when

the output power is less than 50% rated power. Since the

output power is inversely proportional to the switching

frequency, more circuit losses would happen at light load.

The circuit efficiency drops to 0.84 at 30 % rated power.

TABLE II. CIRCUIT PARAMETERS.

Filter Inductor Lm 2.16 mH

Filter Capacitor Cm 0.47 μF

Boost Inductor Lp 0.76 mH

DC-Link Capacitors Cdc 100 μF

Buck Inductor Lb 2.14 mH

Buck Capacitor Co 100 μF

Active Switches S1, S2 IRF840

Diodes D5 MUR460

Fig. 10. Waveforms of vin, iin and ip (vin: 200 V/div, iin, ip: 2 A/div, time: 5

ms/div).

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Fig. 11. Waveforms of Vo and Io (Vo: 100 V/div, Io: 0.1 A/div, time: 5

ms/div).

Fig. 12. Waveforms of ip, and ib (ip, ib: 2 A/div, time: 10 us/div).

(a)

(b)

Fig. 13. Waveforms of vDS1, iS1, vDS2, and iS2 at (a) the peak point and (b)

the zero-crossing point of the input-line voltage (vDS1, vDS2: 200 V/div, iS1,

iS2: 2 A/div, time: 5 us/div).

, rated value (%) o o P P

Fig. 14. Measured power factor, THDi and circuit efficiency for different

output power.

V. CONCLUSIONS

A high efficiency ZVS ac/dc converter that integrates a

boost converter and a buck converter is proposed. By

freewheeling the inductor currents of the converters to flow

through each of the intrinsic diodes of the MOSFETs, both

active switches are turned on at ZVS. It assures high circuit

efficiency. The boost converter is designed to operate at

DCM to perform the function of PFC. It requires that dclink

voltage should be higher than two times of the

amplitude of input voltage. The buck converter further

regulates the dc-link voltage to obtain a stable dc voltage

with low ripple. Experimental results based on the 60-W

prototype circuit show that high circuit efficiency, high

power factor and low THDi can be achieved over a wide

load range. A circuit efficiency of 94.8%, power factor of

0.995 and a THDi of 9.25% are measured at rated output

power.

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10.1109/TPEL.2015.2439963, IEEE Transactions on Power Electronics

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI

10.1109/TPEL.2015.2439963, IEEE Transactions on Power Electronics

Manuscript received August 18, 2014; revised November 27, 2014 and

February 11, 2015; accepted May 25, 2015. This work was supported by

the National Science Council (NSC) of Taiwan, under Grant NSC 102-

2221-E-214 -027.

The authors are with the Department of Electrical Engineering, I-Shou

University, Kaohsiung 84001, Taiwan (e-mail: chchang@isu.edu.tw;

cacheng@isu.edu.tw; enchihchang@isu.edu.tw; hlcheng@isu.edu.tw and

poen_yang@hotmail.com).

An Integrated High-Power-Factor Converter with

ZVS Transition

Chien-Hsuan Chang, Member, IEEE, Chun-An Cheng, Member, IEEE, En-Chih Chang, Hung-Liang Cheng, Member,

IEEE, and Bo-En Yang

Abstract—This paper proposes a single-phase high-powerfactor ac/dc converter with soft-switching characteristic. The circuit topology is derived by integrating a boost converter and a buck converter. The boost converter performs the function of power-factor correction (PFC) to obtain high power factor and

low current harmonics at the input line. The buck converter further regulates the dc-link voltage to provide a stable dc output voltage. Without using any active-clamp circuit or snubber circuit, the active switches of the proposed converter can achieve zero-voltage switching-on (ZVS) transition together with high power factor that satisfies the IEC 61000-3-2 standards over a wide load range from 30% to 100% rated

power. The steady-state analysis is developed and a design example is provided. A prototype circuit of 60 W was built and tested. Experimental results verify the feasibility of the proposed circuit with satisfactory performance.

Keywords—Boost converter, buck converter, power-factor

correction (PFC), zero-voltage switching-on (ZVS).

I. INTRODUCTION

Nowadays, switching-mode ac/dc converters have been

widely used in many off-line appliances, such as dc

uninterruptible power supply, telecommunications power

supply, LED driver etc. [1-2]. The increasing amount urges

researchers to develop more efficient, smaller size, and low

cost ac/dc converters. In order to meet the standards of

harmonic regulation such as IEC 61000-3-2 Class D and

IEEE 519, a power-factor corrector is usually required.

Owing to the advantages of simple circuit topology and

easy control, boost or buck-boost converters have been

widely served as power-factor correctors [3-6]. In order to

achieve unity power factor, it requires the output voltage of

both converter be higher than the amplitude of the ac line

voltage. Therefore, high-power-factor ac/dc converters

usually consist of two stages. The first one is an ac-to-dc

stage which performs the function of PFC and the second

one is a dc-to-dc stage used to supply stable dc voltage to

the load [7-10]. In spite of their good performance, the

circuit efficiency of two-stage approaches is impaired since

it takes two energy-conversion processes which inevitably

introduce some losses including switching loss, conduction

loss and magnetic core loss. Besides the two-stage

approaches, the Cuk and the Sepic converters can also

achieve high power factor and regulate the output voltage

[11-14]. The Cuk converter is a combination of boost and

buck converter and the Sepic converter is a combination of

boost and buck-boost converter. Both converters have the

advantage of simple circuit topology since they only use one

active switch and one diode. High power factor can be

achieved by operating the boost converter either at DCM or

continuous conduction mode (CCM). The buck or buckboost

converter can further regulate the output voltage of the

boost converter to obtain a smooth dc voltage. However, the

output voltage of the boost converter is usually higher than

the amplitude of the AC line voltage. Before turning on the

active switch, the output voltage is across its parasitic

capacitor. The energy stored in the parasitic capacitor is

discharged at turning on the active switch, resulting in high

switching losses and a high spike current. The boost, Cuk

and Sepic converters can also be operated at critical

conduction mode (CRM) to obtain high power factor.

Synchronous rectification (SR) technique is popularly

applied while operating these converters at CRM [15-17]. A

MOSFET is used to replace the freewheel diode, and hence

the conduction loss is effectively reduced. Furthermore, by

extending the turn-on time of the synchronous switch, the

inductor current would decline to negative. This negative

inductor current can discharge the parasitic capacitance of

the main switch to provide ZVS. However, SR technique

requires additional control circuitry to adjust the timing of

the switches. Moreover, the switching frequency is not

constant, but varies a wide range within an AC line period

while operating these converters at CRM.

In pursuit of high efficiency and high power factor,

researchers have presented many single-stage ac/dc

converters based on the integration of a PFC stage and a dcto-

dc stage [18-29]. By sharing one or two active switches,

the single-stage approaches have the advantages of less

component count, simply circuit topology and cost effective.

As compared with two-stage approaches, the circuit

efficiency is improved since only one power-conversion

process is required. Among them, some single-stage

approaches integrate a PFC converter with a full-bridge or

half-bridge resonant converters. These resonant converters

can operate with ZVS if the resonant circuits present

inductive, i.e. the switching frequency is above the resonant

frequency. Moreover, ZVS can be achieved within a wide

load range by variable-frequency control or asymmetrical

pulse-width modulation (APWM). Although, these

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topologies can effectively eliminate switching losses by

switching the active switches near the resonance frequency

to achieve ZVS, operating active switches near the

resonance frequency companies with high resonant current

and results in more conduction losses. The single-stage

approaches that integrate two PWM converters also have

some drawbacks that restrict further improving the circuit

efficiency. The major problem is that the active switches

usually operate in hard switching. An active switch that

operates at hard switching not only generates high switching

losses but also introduces high voltage and current stresses

on circuit components, resulting in poor efficiency and low

circuit stability.

The switching loss is theoretically proportional to the

switching frequency. Now that hard-switching operation has

serious switching losses in the active switches, it prevents

converters from using small magnetic components and

capacitors by increasing the switching frequency. In order to

solve the problem of hard switching, some soft-switching

techniques which adopt active-clamp circuit or snubber

circuit have been proposed [30-36]. These soft-switching

techniques have substantially eliminated the switching loss.

However, these techniques need to use additional auxiliary

switch, diode and reactive components to make the active

switches turn on at zero-voltage. It adds the circuit

complexity and overall cost. Besides, another conduction

losses resulting from the circulating current in the activeclamp

circuit would happen.

In this paper, a new ac/dc converter featuring ZVS with

simple control is presented and analyzed. This paper is

organized as follows. Section II presents the derivation of

the circuit configuration and the circuit operation for the

different operation modes. Detail circuit analysis and design

equations are provided in Section III. In Section IV, a 60-W

prototype circuit is built, and tested to verify the feasibility

of the proposed converter. Finally, some conclusions are

given in Section V.

II. CIRCUIT CONFIGURATION AND OPERATION MODES

Fig. 1 is an example of a high-power-factor ac/dc

converter with a two-stage circuit topology. It consists of a

boost converter and a buck converter. This two-stage

converter can realize high-power factor with a wide load

range. Nevertheless, both active switches of the converter

operate at hard-switching condition, resulting in high

switching losses and high current and voltage stresses.

In order to solve the problem resulting from hard

switching, a new ac/dc converter is proposed, as shown in

Fig. 2. The circuit topology is derived by relocating the

positions of the semiconductor devices in Fig. 1. Here,

MOSFETs S1 and S2 play the roles of active switches and

the antiparallel diodes DS1 and DS2 are their intrinsic body

diodes, respectively. The proposed circuit mainly consists of

a low-pass filter (Lm and Cm), a diode-bridge rectifier (D1-

D4), a boost converter and a buck converter. The boost

converter is composed of Lp, DS1, S2 and Cdc and the buck

Fig. 1. Two-stage ac/dc converter.

Fig. 2. Circuit topology of the proposed ac/dc converter.

converter is composed of Lb, D5, DS2, S1 and Co. Both

converters operate at a high-switching frequency, fs. The

boost converter performs the function of PFC. When it

operates at discontinuous-conduction mode (DCM), the

average value of its inductor current in every high-switching

cycle is approximately a sinusoidal function [5]. The lowpass

filter is used to remove the high frequency current of

the inductor current. By this way, the boost converter can

waveshape the input line current to be sinusoidal and in

phase with the input line voltage. In other word, high power

factor and low total current harmonic distortion (THDi) can

be achieved. The buck converter further regulates the output

voltage of the boost converter to supply stable dc voltage to

the load. It is also deigned to operate at DCM for achieving

ZVS based on the reason that will be discussed in the final

of this section.

Two gate voltages, vGS1 and vGS2 from a half-bridge gate

driver integrated circuit (IC) are used to alternately turn S1

and S2 on and off. These voltages are complementary

rectangular-wave voltages. In order to prevent both active

switches from cross conducting, there is a short non-overlap

time defined as “dead time”. In the dead time, vGS1 and vGS2

are at a low level. Neglecting the short dead time, the duty

cycle of vGS1 and vGS2 is 0.5.

For simplifying the circuit analysis, the following

assumptions are made:

1) The semiconductor devices are ideal except for the

parasitic output capacitance of the MOSFETs.

2) The capacitances of Cdc and Co are large enough that

the dc-link voltage Vdc and the output voltage Vo can be

regarded as constant.

At steady state, the circuit operation can be divided into

eight modes in every high-frequency cycle. Fig. 3 shows the

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equivalent circuits for each of the operation modes. In these

equivalent circuits, the low-pass filter and the diode rectifier

are represented by the rectified voltage vrec. Fig. 4 illustrates

the theoretical waveforms in each mode for the case of

operating the buck converter at DCM. The circuit operation

is described as follows.

A. Mode I (t0 < t < t1)

Prior to Mode I, S1 is at “ON” state. The boost-inductor

current ip is zero and the dc-link capacitor supplies the buckinductor

current ib which flows through S1, D5, Lb and Co.

This mode starts when S1 is turned off by the gate voltage,

vGS1. The time interval of this mode is the turn-off transition.

At the beginning of this mode, ib is diverted from S1 to flow

through the output capacitors CDS1 and CDS2. CDS1 and CDS2

are charged and discharged, respectively. As the voltage

across CDS2 (vDS2) decreases to be lower than the rectified

input voltage vrec, the boost-inductor current ip starts to

increase. When vDS2 reaches -0.7 V, DS2 turns on and Mode I

ends.

B. Mode II (t1 < t < t2)

At the beginning of Mode II, voltage vDS2 is maintained at

about -0.7 V by the antiparallel diode DS2. After the short

dead time, S2 is turned on by the gate voltage, vGS2. If the

on-resistance of S2 is small enough, most of ib will flow

through S2 in the direction from its source to drain.

Neglecting this small value of vDS2, the voltage across Lb and

Lp are equal to

vb t Vo (1)

2 p rec m L v t v t V sin f t (2)

Fig. 3. Operation modes.

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where fL and Vm are the frequency and the amplitude of the

input line voltage, respectively. Since the time interval of

Mode I is very short, ib can be expressed as:

0 0 ( ) ( ) o

b b

b

V

i t i t t t

L

(3)

From (3), ib decreases from a peak value. The boost

converter is designed to operate at DCM, therefore ip

increases linearly from zero with a rising slope that is

proportional to vrec.

0 0

sin 2

( ) rec m L

p

p p

v V f t

i t t t t t

L L

(4)

In Mode II, ib is higher than ip. Current ib has two loops.

Parts of ib flow through S2 and the rest are equal to ip and

flow through the line-voltage source, diode rectifier and Lp.

This mode ends when ip rises to become higher than ib.

C. Mode III (t2 < t < t3)

In Mode III, ip is higher than ib. Current ip has two loops.

Parts of ip are equal to ib and flow into the buck converter,

while the rest flow through S2. The current direction in S2 is

naturally changed, i.e. from drain to source. The voltage and

current equations for vb, vp, ib and ip are the same as (1) –

(4). Current ib decreases continuously. On the contrary, ip

keeps increasing. Since the buck converter is designed to

operate at DCM, ib will decrease to zero at the end of this

mode.

D. Mode IV (t3 < t < t4)

In this mode, S2 remains on to carry ip. Beacuse ib is zero,

the buck converter is at “OFF” state and the output capacitor

Co supplies current to load. When S2 is turned off by the

gate voltage vGS2, Mode IV ends.

E. Mode V (t4 < t < t5)

Current ip reaches a peak value at the time instant of

turning off S2. For maintaining flux balance in Lp, ip will be

diverted from S2 to flow through CDS1 and CDS2 when S2 is

turned off. CDS1 and CDS2 are discharged and charged,

respectively. Current ib is zero at the beginning of this mode,

and will start to increase when the voltage across CDS1 (vDS1)

decreases to be lower than Vdc-Vo, that is the voltage across

Lb becomes positive. As vDS1 reaches -0.7 V, DS1 turns on

and Mode V ends.

F. Mode VI (t5 < t < t6)

At the beginning of Mode VI, vDS1 is maintained at about

-0.7 V by the antiparallel diode DS1. After the short dead

time, S1 is turned on by vGS1. If the on-resistance of S1 is

small enough, most of ip will flow through S1 in the

direction from its source to drain. Neglecting this small

value of vDS1, the voltage imposed on Lp and Lb can be

respectively expressed as

vp t vrec t Vdc Vm sin 2 fLt Vdc (5)

b dc o v t V V . (6)

For a boost converter, the dc-link voltage Vdc is higher

than the rectified voltage vrec. Neglecting the short turning

off transition of S2, ip can be expressed as:

4 4

m 2 L dc

p p

p

V sin f t V

i t i t t t

L

(7)

On the contrary, the voltage across Lb is positive to make

ib rise from zero.

4 ( ) dc o

b

b

V V

i t t t

L

(8)

In Mode VI, ip is higher than ib. There are two loops for

ip. Parts of ip flow through S1 to charge the dc-link capacitor

Cdc and the rest are equal to ib and flow into the buck

converter. This mode ends when ib rises to become higher

than ip.

G. Mode VII (t6 < t < t7)

In Mode VII, ib is higher than ip. There are two loops for

ib. Parts of ib are equal to ip and flow into the boost converter,

while the rest flow through S1. The current direction in S1 is

naturally changed, i.e. from drain to source. The voltage and

current equations for vp, vb, ip and ib are the same as (5) – (8).

Current ib increases continuously while ip keeps decreasing.

The circuit operation enters next mode as soon as ip

decreases to zero.

H. Mode VIII (t7 < t < t8)

S1 remains on and ib keeps increasing. This mode ends at

the time when vGS1 becomes a low level to turn off S1 and,

the circuit operation returns to Mode I of the next highfrequency

cycle.

Based on the circiuit operation, prior to turning on one

active switch, the output capactance is discharged to about

0.7 V by the inductor current. Then, the intrinsic body diode

of the active switch turns on to clamp the active voltage at

nearly zero voltage. By this way, each active switch

achieves ZVS operation.

The reason for operating the buck converter at DCM is

explained below. In operation Mode II, ip rises and ib

decreases. It should be noted that ip rises in proportional to

the input voltage and has a small peak in the vicinity of

zero-cross point of the input voltage. If the buck converter is

operated at continuous-conduction mode (CCM), ib could

keep higher than ip. On this condition, the circuit operation

would not enter into Mode III and Mode IV, and vDS1 is

maintain at about Vdc. When S1 is turned on, ib is diverter

from S2 to S1. CDS1 is discharged at a high voltage of Vdc,

resulting a spike current and high switching losses.

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Fig. 4. Theoretical waveforms of the proposed converter.

III. CIRCUIT ANALYSIS

According to the circuit operation in the previous section,

it can be seen that the antiparallel diode of the active switch

of one converter serves as the freewheeling diode of the

other converter. In spite of it, the feathers of the boost and

the buck converter can be retained. Therefore, the two

converters can be analyzed separately.

A. Boost-Converter-Type Power-Factor Corrector

The boost-inductor current ip increases from zero and

reaches a peak value at the end of Mode IV. In practical, the

frequency of the input line voltage, fL, is much lower than

that of the converters. It is reasonable to consider the

rectified input voltage vrec as a constant over a highfrequency

cycle. From (4), the peak values of ip can be

expressed as

4 0

2 2

2

m L m L s

p,peak

p p

V sin f t V sin f t T

i t t t

L L

(9)

where Ts is the high-frequency switching period. At the

beginning of Mode V, ip start to decrease. Eq. (7) can be

rewritten as

t . T .

L

V sin f t V

L

V sin f t T

i t s

p

m L dc

p

m L s

p 0 5

2

2

2

(10)

From (10), the duration of the interval during which ip

decreases from the peak value to zero is described by

.

V V sin f t

. T V sin f t

t t

dc m L

s m L

p,off

2

0 5 2

(11)

In order to operate the boost converter at DCM, tp,off (t)

must always be less than half of the switching period.

, 0.5 . p off s t t T (12)

Combining (11) and (12), Vdc should be high enough to

ensure DCM operation over an entire input line-frequency

cycle, as follows:

2 . dc m V V (13)

The conceptual waveform of ip is shown in Fig. 5. It is

noted that the peak values of ip follow a sinusoidal envelope.

The average value of ip over a high-frequency cycle is given

by

0 5

2

s p,off p,peak

p

s

. T t t i t

i t .

T

(14)

It results in (15) by substituting (9) and (11) into (14).

2 1

8 1 1 2

m L

p

p s

L

V sin f t

i t

L f sin f t

k

(15)

where the index k is defined as

dc .

m

k V

V

(16)

Considering the effect of diode-bridge rectification and

the low-pass filter that can remove the high-frequency

contents of ip, the input current iin is equal to the average

value of ip, as follows:

2 1

8 1 1 2

m L

in

p s

L

V sin f t

i t .

L f sin f t

k

(17)

It can be seen that iin will be close to a sinusoidal

waveform at a large value of k. In other words, Vdc should be

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high enough to have a sinusoidal input current. Using (16)

and (17), the input power can be obtained by taking average

of the instantaneous product of the input voltage and current

over one line-frequency cycle.

2

0

1 2 2

8

m

in m L in L

p s

V

P Vsin ft i td ft y

L f

(18)

(18)

where y is expressed in (19), as follows: [4]

2 3

1 2

0 2

= 1 2 1 2 1 1 1

y sin d k sin k k

sin k k

k

(18)

(19)

Assuming a circuit efficiency of , the output power can

be expressed as

2

8

m

o

p s

V

P y

L f

(20)

The root-mean-squared value of the input current is

calculated by using (17).

2

0

1 2 =

8

m

in,rms in

p s

V

I i t d ft z

L f

(21)

where z is expressed in (22), as follows: [5]

Fig. 5. Conceptual waveform of the boost-inductor current.

Fig. 6. Power factor versus k. (k =Vdc/Vm).

2

0

4 3 2

2 1

2 2 3 2 2

1 1

2 2 2 1 =

1 1 2 1

z sin d

sin

k

k k k k tan

k k k

(22)

Since the input voltage is purely sinusoidal, the power

factor defined as the ratio of input power to the product of

the root-mean-squared values of input voltage and current

can be obtained by using (18) and (21).

= 2

2

in

m

in,rms

PF P y .

V I z

(23)

The power factor as a function of k is calculated and

plotted in Fig. 6 by using (19), (22) and (23). As shown,

high power factor can be achieved at a high-valued k. From

(13), the index k should be higher than 2. In this situation,

power factor is better than 0.99.

B. Buck Converter

For DCM operation, ib rises from zero. Neglecting the

short transition of turning off S2, the rising time of ib is equal

to 0.5Ts. From (8), ib has a peak value that is equal to

,

2

dc o S

b peak

b

V V T

i

L

(24)

The current ib starts to decrease when S1 is turned off. By

using (3), the time duration for ib decreasing from the peak

value to zero is given by

, 2

dc o S

b off

o

V V T

t

V

(25)

For fulfilling DCM operation, tb,off should be less than

0.5Ts. This leads to

2 dc o V V (26)

AS shown in Fig. 4, ib is with a triangular waveform and

its average value can be derived by using (24) and (25).

, , (0.5 ) ( )

2 8

s b off b peak dc o dc s

b

s bo

T t i V V V T i

T LV

(27)

At steady-state operation, the average value of ib will be

equal to the output current.

o

b o

o

V

i I

R

(28)

Combining (27) and (28), the formula of Lb for DCM

operation is derived, as follows:

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( ) ( )

8 8

dc o dc s dc o dc

b

o o o s

V V V T V V V

L

V I P f

(29)

IV. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS

An illustrative example for driving sixty 1-W highbrightness

LEDs is provided. These LEDs are connected in

series. The rated voltage and current of each LED are 3.6 V

and 0.28 A, respectively. Table I lists the circuit

specifications. The input voltage is 110 Vrms ± 10%. The

switching frequency is 50 kHz at rated power operation. In

this design example, both converters are designed to operate

at DCM. The circuit parameters are designed as follows.

A. Parameters Design

From (13) and (26), Vdc should be limited between 2Vm to

2Vo. Taking the consideration of 10% input voltage

fluctuation, Vdc is chosen to be

360 V. dc V

In this case, k is calculated to be 2.3. From Fig. 6, the

power factor higher than 0.99 can be expected.

Assuming 95% circuit efficiency, Lp and Lb can be

calculated by using (18) and (29) respectively.

2 3

1 2

3 2

0 95 155 1 2 1 2

8 50 10 60 1

=0.76 mH ( 2 3)

p

L . k sin k k

k k

k .

3

(360 216) 360 2.14 mH.

b 8 216 0.28 50 10 L

Lm and Cm are designed to perform as a low-pass filter to

filter out the high-frequency components of the boostinductor

ip. By rule of thumb, the natural frequency of a

low-pass filter is about 1 decade below the switching

frequency. Here, the natural frequency is designed to be 5

kHz, and Lm and Cm are determined to be

2 16 mH, 0 47 μF. m m L . C .

B. Dimming operation

The LED had been tested at different power. Fig. 7 shows

its V-I curve. Based on these experimental results, the LED

voltage as a function of output power can be expressed as

3 2

0 0 0 0 0003 0 0407 2 4742 150 oV . P . P . P (30)

For dimming operation, the output voltage is adjusted to

regulate the LED current. As shown in (20), Po is functions

of y and fs. From (19), the parameter y would vary slightly

when k is in the neighbor of 2.3. Hence, it is reasonable to

assume that Po is inversely proportional to the switching

frequency. By using (29), Vdc can be expressed as

2

2 32

o o b o s

dc

V V L P f

V

(31)

Fig. 8 shows the theoretical curves of Vdc and fs versus Po.

Using (30) and (31), if the LED is dimmed from 100% to

30% rated power, the switching frequency would vary form

50 kHz to 167 kHz. The dc-link voltage and the output

voltage vary form 360 V to 336 V and 216 V to 183.1 V.

During the dimming operation, (13) and (26) are satisfied to

ensure both converters operate at DCM. In other words, the

inductor current of one converter will decline to zero before

turning off the active switch of the other converter. It

ensures the intrinsic body diode of one active switch will be

turned on to flow the inductor current when the other active

switch is turned off. By this way, ZVS operation can be

achieved within the dimming range.

A prototype circuit is built and tested. Table II lists the

circuit parameters. Since the I–V characteristic of an LED is

similar to that of a diode, a small variation in the LED

voltage will result in a significant change in its current.

Generally, constant current control with low-frequency

pulse-width modulation is usually used to realize LED

TABLE I. CIRCUIT SPECIFICATIONS.

Input Line Voltage, vin 110 Vrms±10%, 60 Hz

High Switching Frequency, fS1, f S2 50 kHz

Output Power, Po 60 W

Output Voltage, Vo 216 V (= 3.6 V 60)

Output Current, Io 0.28 A

Fig. 7. V-I curve of tested LED.

, rated value (%) o o P P

Fig. 8. Vdc and fs versus Po.

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Fig. 9. Control circuit.

dimming. However, it requires complicated circuit to

precisely detect the peak value of the pulsed LED current. In

this prototype circuit, sixty LEDs are connected in series

and then, more voltage change is needed to dim the LED. It

makes the series-connected LEDs can be easily dimmed by

voltage control. Fig. 9 shows the closed-loop control circuit

that mainly consists of a double-ended controller (L6599)

for half-bridge topology and a photocoupler (PC817). The

L6599 provides a pair of gate voltages with fixed dead time

(0.3μs) to drive both active switches. Output voltage

regulation is obtained by modulating the switching

frequency. The feedback signal of the output voltage is

transferred to pin 4 of the L6599 via the phototransistor of

the optocoupler to modulate the switching frequency. The

output voltage is varied by adjusting the variable resistor

VR1 for dimming LED.

Fig. 10 to Fig. 13 shows voltage and current waveforms

that are measured at rated output power. Fig. 10 shows the

waveforms of the input voltage, the input current and the

boost-converter current. It is seen that the boost converter

operates at DCM over an entire cycle of the line voltage.

The input current is close to a sinusoidal waveform. Besides,

the input current and the input voltage are in phase with

each other. High power factor and low THDi can be

achieved. The measured power factor and THDi are 0.995

and 9.25%, respectively. It complies with the standards of

IEC 61000-3-2 class D. Fig. 11 shows the waveforms of the

output voltage and output current. The measured values well

satisfy the theoretical prediction. The inductor-current

waveforms of both converters are shown in Fig. 12. Both

converters operate at DCM. Fig. 13 shows the voltage and

current waveforms of the active switches which are

measured at the peak point and the zero-crossing point of

the input-line voltage, respectively. As shown, both active

switches are switched on at nearly zero voltage. With ZVS

operation at both active switches, the circuit efficiency is as

high as 94.8%. It is noted that ip is almost zero at the zerocrossing

point of the AC voltage and cannot fully discharge

the output capacitance of S1 within the deadtime. When S1 is

turned on at the end of deadtime, the remaining charges in

the output capacitance rapidly flow through S1, resulting in a

spike current, as shown in Fig. 13 (b). Since the non-ZVS

operation only happens at the zero-crossing point of the AC

input, it insignificantly impairs the circuit efficiency. In

order to know how much efficiency can be improved with

proposed circuit, a two-stage boost+buck prototyped circuit

is built and tested with the same circuit specification as the

proposed circuit. At 50 kHz switching frequency, the

measure efficiency of the two-stage circuit is 90.7%.

The measured curves of power factor, THDi and circuit

efficiency over a load range from 30% to 100% rated power

are shown in Fig. 14. Power factor is close to unity over the

wide load range, while THDi increases dramatically when

the output power is less than 50% rated power. Since the

output power is inversely proportional to the switching

frequency, more circuit losses would happen at light load.

The circuit efficiency drops to 0.84 at 30 % rated power.

TABLE II. CIRCUIT PARAMETERS.

Filter Inductor Lm 2.16 mH

Filter Capacitor Cm 0.47 μF

Boost Inductor Lp 0.76 mH

DC-Link Capacitors Cdc 100 μF

Buck Inductor Lb 2.14 mH

Buck Capacitor Co 100 μF

Active Switches S1, S2 IRF840

Diodes D5 MUR460

Fig. 10. Waveforms of vin, iin and ip (vin: 200 V/div, iin, ip: 2 A/div, time: 5

ms/div).

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Fig. 11. Waveforms of Vo and Io (Vo: 100 V/div, Io: 0.1 A/div, time: 5

ms/div).

Fig. 12. Waveforms of ip, and ib (ip, ib: 2 A/div, time: 10 us/div).

(a)

(b)

Fig. 13. Waveforms of vDS1, iS1, vDS2, and iS2 at (a) the peak point and (b)

the zero-crossing point of the input-line voltage (vDS1, vDS2: 200 V/div, iS1,

iS2: 2 A/div, time: 5 us/div).

, rated value (%) o o P P

Fig. 14. Measured power factor, THDi and circuit efficiency for different

output power.

V. CONCLUSIONS

A high efficiency ZVS ac/dc converter that integrates a

boost converter and a buck converter is proposed. By

freewheeling the inductor currents of the converters to flow

through each of the intrinsic diodes of the MOSFETs, both

active switches are turned on at ZVS. It assures high circuit

efficiency. The boost converter is designed to operate at

DCM to perform the function of PFC. It requires that dclink

voltage should be higher than two times of the

amplitude of input voltage. The buck converter further

regulates the dc-link voltage to obtain a stable dc voltage

with low ripple. Experimental results based on the 60-W

prototype circuit show that high circuit efficiency, high

power factor and low THDi can be achieved over a wide

load range. A circuit efficiency of 94.8%, power factor of

0.995 and a THDi of 9.25% are measured at rated output

power.

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