Atmel AVR:
Device
overview
The
AVR is a modified Harvard architecture machine
where program and data are stored in separate physical memory systems that
appear in different address spaces, but having the ability to read data items
from program memory using special instructions.
Device architecture
Flash,
EEPROM, and
SRAM are
all integrated onto a single chip, removing the need for external memory in
most applications. Some devices have a parallel external bus option to allow
adding additional data memory or memory-mapped devices. Almost all devices
(except the smallest TinyAVR chips) have serial interfaces, which can be used
to connect larger serial EEPROMs or flash chips.
Program memory
Program
instructions are stored in
non-volatile flash memory.
Although the MCUs are 8-bit, each instruction takes one or two 16-bit words.
The
size of the program memory is usually indicated in the naming of the device
itself (e.g., the ATmega64x line has 64 kB of flash while the ATmega32x
line has 32 kB).
There
is no provision for off-chip program memory; all code executed by the AVR core
must reside in the on-chip flash. However, this limitation does not apply to
the AT94 FPSLIC AVR/FPGA chips.
Internal data memory
I/O Registers in AVR
Each
port consists of three registes: DDRx, PORTx and PINx.
·
DDRx :
Data direction register.
·
PORTx :
Output port register. Used only for output.
·
PINx :
Input register. Used only for input.
Pin toggling
with PINx: "writing a logic one to PINx n bit toggles the value of PORTx n bit, independent on the value of DDRx n".[6]This may not be
true for all AVR devices, check the datasheet of the device.
EEPROM
Almost
all AVR microcontrollers have internal
EEPROM for semi-permanent data storage. Like
flash memory, EEPROM can maintain its contents when electrical power is
removed.
In
most variants of the AVR architecture, this internal EEPROM memory is not
mapped into the MCU's addressable memory space. It can only be accessed the
same way an external peripheral device is, using special pointer registers and
read/write instructions which makes EEPROM access much slower than other
internal RAM.
However,
some devices in the SecureAVR (AT90SC) family
[7] use a special EEPROM mapping to the
data or program memory depending on the configuration. The XMEGA family also
allows the EEPROM to be mapped into the data address space.
Since
the number of writes to EEPROM is not unlimited — Atmel specifies 100,000 write
cycles in their datasheets — a well designed EEPROM write routine should
compare the contents of an EEPROM address with desired contents and only
perform an actual write if the contents need to be changed.
Note
that erase and write can be performed separately in many cases, byte-by-byte,
which may also help prolong life when bits only need to be set to all 1s
(erase) or selectively cleared to 0s (write).
Program execution
Atmel's AVRs have
a two stage, single level
pipeline design.
This means the next machine instruction is fetched as the current one is
executing. Most instructions take just one or two clock cycles, making AVRs
relatively fast among
eight-bit microcontrollers.
The
AVR processors were designed with the efficient execution of
compiled C code
in mind and have several built-in pointers for the task.
Instruction set
·
Pointer
registers X, Y, and Z have addressing capabilities that are
different from each other.
·
Register locations R0 to R15 have
different addressing capabilities than register locations R16 to R31.
·
I/O ports 0 to 31 have different
addressing capabilities than I/O ports 32 to 63.
·
CLR affects flags, while SER does
not, even though they are complementary instructions. CLR set all bits to zero
and SER sets them to one. (Note that CLR is pseudo-op for EOR R, R; and SER is
short for LDI R,$FF. Math operations such as EOR modify flags while
moves/loads/stores/branches such as LDI do not.)
·
Accessing read-only data stored in
the program memory (flash) requires special LPM instructions; the flash bus is
otherwise reserved for instruction memory.
Additionally, some chip-specific differences affect code
generation. Code pointers (including return addresses on the stack) are two
bytes long on chips with up to 128 kBytes of flash memory, but three bytes long
on larger chips; not all chips have hardware multipliers; chips with over 8
kBytes of flash have branch and call instructions with longer ranges; and so
forth.
The mostly regular instruction set makes programming it
using C (or even Ada) compilers fairly straightforward. GCC has included AVR support for
quite some time, and that support is widely used. In fact, Atmel solicited
input from major developers of compilers for small microcontrollers, to
determine the instruction set features that were most useful in a compiler for
high-level languages.
MCU speed
The AVR line can
normally support clock speeds from 0 to 20 MHz, with some devices reaching
32 MHz. Lower powered operation usually requires a reduced clock speed.
All recent (Tiny, Mega, and Xmega, but not 90S) AVRs feature an on-chip
oscillator, removing the need for external clocks or resonator circuitry. Some
AVRs also have a system clock prescaler that can divide down the system clock
by up to 1024. This prescaler can be reconfigured by software during run-time,
allowing the clock speed to be optimized.
Since
all operations (excluding literals) on registers R0 - R31 are single cycle, the
AVR can achieve up to 1
MIPS per
MHz, i.e. an 8 MHz processor can achieve up to 8 MIPS. Loads and stores
to/from memory take two cycles, branching takes two cycles. Branches in the
latest "3-byte PC" parts such as ATmega2560 are one cycle slower than
on previous devices.
Development
AVRs have a large following due to the free and inexpensive
development tools available, including reasonably priced development boards and
free development software. The AVRs are sold under various names that share the
same basic core, but with different peripheral and memory combinations.
Compatibility between chips in each family is fairly good, although I/O
controller features may vary.
Features
·
Multifunction, bi-directional general-purpose
I/O ports with configurable, built-in pull-up
resistors
·
Multiple internal oscillators,
including RC oscillator without external parts
·
Internal, self-programmable
instruction flash memory up to 256 kB
(384 kB on XMega)
·
Optional boot code section with
independent lock bits for protection
·
On-chip debugging (OCD) support
through JTAG or debugWIRE on most devices
·
The JTAG signals (TMS, TDI, TDO, and
TCK) are multiplexed on GPIOs. These pins can be configured to
function as JTAG or GPIO depending on the setting of a fuse bit, which can be
programmed via ISP or HVSP. By default, AVRs with JTAG come with the JTAG
interface enabled.
·
debugWIRE uses
the /RESET pin as a bi-directional communication channel to access on-chip
debug circuitry. It is present on devices with lower pin counts, as it only
requires one pin.
·
Internal data EEPROM up
to 4 kB
·
Internal SRAM up to 16 kB (32 kB on
XMega)
·
External 64 kB little endian
data space on certain models, including the Mega8515 and Mega162.
·
The external data space is overlaid
with the internal data space, such that the full 64 kB address space does
not appear on the external bus and accesses to e.g. address 010016 will
access internal RAM, not the external bus.
·
In certain members of the XMega
series, the external data space has been enhanced to support both SRAM and
SDRAM. As well, the data addressing modes have been expanded to allow up to
16 MB of data memory to be directly addressed.
·
AVRs generally do not support
executing code from external memory. Some ASSPs using the AVR
core do support external program memory.
·
8-bit and 16-bit timers
·
PWM output (some devices have an
enhanced PWM peripheral which includes a dead-time generator)
·
Input capture that
record a time stamp triggered by a signal edge
·
Analog comparator
·
A variety of serial interfaces,
including
·
I²C compatible
Two-Wire Interface (TWI)
·
Synchronous/asynchronous serial
peripherals (UART/USART) (used with RS-232, RS-485, and
more)
·
Universal Serial Interface (USI) for
two or three-wire synchronous data transfer
·
Multiple power-saving sleep modes
·
Lighting and motor control (PWM-specific) controller models
·
Proper full-speed (12 Mbit/s)
hardware & Hub controller with embedded AVR.
·
Also freely available low-speed (1.5
Mbit/s) (HID) bitbanging software
emulations
·
Low-voltage devices operating down
to 1.8 V (to 0.7 V for parts with built-in DC–DC upconverter)
·
picoPower devices
·
DMA controllers and "event
system" peripheral communication.
·
Fast cryptography support for AES and DES
Programming interfaces
ISP
6- and 10-pin
ISP header diagrams
The
in-system programming (ISP) programming method is
functionally performed through
SPI, plus some twiddling of the Reset
line. As long as the SPI pins of the AVR are not connected to anything
disruptive, the AVR chip can stay soldered on a
PCB while
reprogramming. All that is needed is a 6-pin connector and programming adapter.
This is the most common way to develop with an AVR.
The Atmel AVR ISP
mkII device connects to a computer's USB port and performs in-system
programming using Atmel's software.
AVRDUDE (AVR
Downloader/UploaDEr) runs on
Linux,
FreeBSD, Windows, and
Mac OS X, and
supports a variety of in-system programming hardware, including Atmel AVR ISP
mkII, Atmel JTAG ICE, older Atmel serial-port based programmers, and various
third-party and "do-it-yourself" programmers.
[8]
PDI
The Program and
Debug Interface (PDI) is an Atmel proprietary interface for external
programming and on-chip debugging of XMEGA devices. The PDI supports high-speed
programming of all non-volatile memory (NVM) spaces; flash, EEPROM, fuses,
lock-bits and the User Signature Row. This is done by accessing the XMEGA NVM
controller through the PDI interface, and executing NVM controller commands.
The PDI is a 2-pin interface using the Reset pin for clock input (PDI_CLK) and
a dedicated data pin (PDI_DATA) for input and output.
Bootloader
ost AVR models can reserve a bootloader region,
256 B to 4 KB, where re-programming code can reside. At reset, the
bootloader runs first, and does some user-programmed determination whether to
re-program, or jump to the main application. The code can re-program through
any interface available, it could read an encrypted binary through an Ethernet
adapter like PXE.
Atmel has application notes and code pertaining to many bus interfaces.
Features:
• High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family
• Advanced RISC Architecture
– 131 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– 4/8/16/32KBytes of In-System Self-Programmable Flash program memory
– 256/512/512/1KBytes EEPROM
– 512/1K/1K/2KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/100 years at 25C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel® QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix® acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
– 6-channel 10-bit ADC in PDIP Package
Temperature Measurement
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and
Extended Standby
Atmel 8-bit Microcontroller with 4/8/16/32KBytes In-System Programmable
Flash
ATmega48A; ATmega48PA; ATmega88A; ATmega88PA;
ATmega168A; ATmega168PA; ATmega328; ATmega328P
1.1.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2
Port B is an
8-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The Port B output buffers have symmetrical drive characteristics
with both high sink and source capability. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are
activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
Depending on the
clock selection fuse settings, PB6 can be used as input to the inverting
Oscillator amplifier and input to the internal clock operating circuit.
Depending on the
clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip
clock source, PB7...6 is used as TOSC2...1 input for the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.The various special features of
Port B are elaborated in ”Alternate Functions of Port B” on page 83 and ”System
Clock and Clock Options”
1.1.4 Port C (PC5:0)
Port C is a
7-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). The PC5...0 output buffers have symmetrical drive characteristics
with both high sink and source capability. As inputs, Port C pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port
C pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
1.1.5 PC6/RESET
If the RSTDISBL
Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical
characteristics of PC6 differ from those of the other pins of Port C.If the
RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a Reset, even
if the clock is not running.
The AVR core
combines a rich instruction set with 32 general purpose working registers. All
the 32 registers are
directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle.
The resulting architecture is more code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers.
The
ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes
of In-System Programmable
Flash with
Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes
SRAM,
23 general
purpose I/O lines, 32 general purpose working registers, three flexible
Timer/Counters with compare modes, internal and external interrupts, a serial
programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial
port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a
programmable Watchdog Timer with internal Oscillator, and five software
selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt
system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power-save mode, the asynchronous timer continues
to run, allowing the user to maintain a timer base while the rest of the device
is sleeping. The ADC Noise Reductionmode stops the CPU and all I/O modules
except asynchronous timer and ADC, to minimize switching noise during
ADC conversions.
In Standby mode, the crystal/resonator Oscillator is running while the rest of
the device is sleeping.This allows very fast start-up combined with low power
consumption.Atmel® offers the QTouch® library for embedding capacitive touch
buttons, sliders and wheels functionality into
AVR® microcontrollers.
The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key
Suppression® (AKS™) technology for unambiguous detection of key events. The
easy-to-use QTouch Suite toolchain allows you to explore, develop and debug
your own touch applications. The device is manufactured using Atmel’s high
density non-volatile memory technology. The On-chip ISP Flash allows the
program memory to be reprogrammed In-System through an SPI serial interface, by
a conventional nonvolatile
memory
programmer, or by an On-chip Boot program running on the AVR core. The Boot
program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash section will continue to
run while the Application Flash section is updated, providing true
Read-While-Write operation.
By combining an
8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the
Atmel ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that
provides a highly flexible and cost effective solution to many embedded control
applications.
The
ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program
and system development tools including: C Compilers, Macro Assemblers, Program
Debugger/Simulators, In-Circuit Emulators, andEvaluation kits.
